Practical Components -TEG WM40-0103JY
Chip Structure
- Base Layer : P-TEOS
- Metal layer : TiN / Al-0.5%Cu
- Passivation Layer : HDP / P-SiN
*TEOS : Tetraethoxysilane
| Specifications | |
| Wafer Size | 8 inch |
| Wafer Thickness | 725±25μm |
| Chip Size | 10.00mm x 8.00mm |
| Function |
Daisy Chain |
| Pad Size | 35μm |
| Passivation Operation | φ10um (Octagon) |
| Number of Pad |
I/O area : 40um pitch x 1200 pad |
| Electrode | Cu Pillar |
| Bump Size | φ20μm |
| Bump Pitch |
1. 40μm |
| Bump Height |
Cu10um+SnAg10um |
| Number of Chip |
312 chips/wafer |
