Chip Structure
- Base Layer : P-TEOS*
- Metal Layer : TiN / AI-0.5%Cu
- Passivation Layer : HDP* / P-SiN
*TEOS : Tetraethoxysilane
*HDP : High Density Plasma
| Specifications | |
| Wafer Size | 8 inch |
| Wafer Thickness | 725±25μm |
| Chip Size | 7.3mm ♦ |
| Pad Pitch | 60μm |
| Function | Daisy Chain |
| Bump Size | - |
| Bump Height | - |
| Number of Pad | 488 pads/chip |
| Number of Chip | 478 chips/wafer |
| Polyimide (Option) | O |
| Evaluation KIT | - |
| ♦ Bottom Side |
