Chip Structure
- Base Layer : P-TEOS*
- Metal Layer : TiN / AI-0.5%Cu
- Passivation Layer : HDP* / P-SiN (option) Polymide
*TEOS : Tetraethoxysilane
*HDP : High Density Plasma
| Specifications | Si | |
| TYPE | A | B |
| Wafer Size | 8 inch | 8 inch |
| Wafer Thickness | 725±25μm | 725±25μm |
| Chip Size | 5.02mm ♦ | 5.02mm ♦ |
| Bump pitch | 200μm | 200μm |
| Function | Daisy Chain | Daisy Chain |
| Pad config | Area | Area |
| Electrode | Ball Mounted Solder Bump | Cu Pillar |
| Pad Size | 100μm ♦ | 100μm ♦ |
| Passivation opening | φ60μm • | φ60μm • |
| Polyimide opening | φ80μm • | φ80μm • |
| UBM Size | φ100μm • | φ90μm • |
| Bump Size | φ100μm • | φ90μm • |
| Scribe width | 100μm | 100μm |
| Number of Pad | 484 pads/chip (22×22) | 484 pads/chip (22×22) |
| Number of Chip | 832 chips/wafer | 832 chips/wafer |
| • Top Side ♦ Bottom Side |
