Flip Chip describes the method of electrically connecting the die to the package carrier. The package carrier, either substrates or leadframe, then provides the connection from the die to the exterior of the package. The interconnection between die and carrier in flip chip packaging is made through a conductive bump that is placed directly on the die surface. The bumped die is then flipped over and placed face down, with the bumps connecting to the carrier. After the die is solderable, underfill is applied between the die and the substrates, around the solder bumps. The underfill is designed to contract the stress in the solder joints caused by the difference in thermal expansion between the silicon die and carrier.
Pac Tech offers a complete set of additional wafer level and backend services including: saw, dice, redistribution, repassivation, backsidelaser mark, backside coating, test die, and assembly. In addition, Pac Tech has the latest in metrology and analytical equipment to help in the development and production proceses, including: x-ray, shear, AOI, ICP, AA, probing, high speed ball pull, chemical analysis, etc…
See below for: Lead-Free Flip Chips



Flip Chips are used in evaluating assembly techniques, board continuity, temperature cycle life test evaluation, underfill processes and other generic needs to be given to the appropriate ‑ux, underll, temperature profile, and pad finish for the assembly. Many companies are developing and qualifying alternative pad finishes as immersion Sn. Lead-Free Flip Chips address the need for environmentally conscious assemblies as well as Alpha particle tolerant packaging.

For kits see PCB310